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Allwinner /D1H /TWI[3] /TWI_DRV_BUS_CTRL

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Interpret as TWI_DRV_BUS_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (sda_moe)sda_moe 0 (scl_moe)scl_moe 0 (sda_mov)sda_mov 0 (scl_mov)scl_mov 0 (sda_sta)sda_sta 0 (scl_sta)scl_sta 0clk_m0clk_n0 (P50)clk_duty 0 (oscl)clk_count_mode

clk_count_mode=oscl, clk_duty=P50

Description

TWI_DRV Bus Control Register

Fields

sda_moe

SDA manual output enable
scl_moe

SCL manual output enable
sda_mov

SDA manual output value
scl_mov

SCL manual output value
sda_sta

SDA current status
scl_sta

SCL current status
clk_m
clk_n
clk_duty

Setting duty cycle of clock as master

0 (P50): 50%

1 (P40): 40%
clk_count_mode

0 (oscl): scl clock high period count on oscl

1 (iscl): scl clock high period count on iscl

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data